1. Field of the Invention
The present invention relates to a drive control apparatus including a watchdog timer.
2. Description of the Related Art
In a drive control system that performs a drive control of a control target apparatus such as an actuator using a central processing unit (hereinafter, referred to as a CPU), a countermeasure to an abnormality or a failure is positively required. Therefore, various techniques of monitoring the CPU to detect the abnormality or the failure are being developed. For example, in the technique disclosed in Patent Document 1, a monitoring IC is provided in addition to the monitor target CPU to be monitored. This monitoring IC monitors operational states of a torque monitoring unit and a signal abnormality diagnosing unit of the CPU and performs a fail-safe control in collaboration with a self-monitoring unit of a microcomputer if the monitoring IC detects an operational abnormality.
However, in this technique disclosed in Patent Document 1, the operational abnormality detected for the CPU by the monitoring IC is limited to specific abnormality such as operational abnormality in a torque monitoring unit and operational abnormality in a signal abnormality diagnosing unit. Further, the technique disclosed in Patent Document 1 has a problem that a wide range of operational abnormality, which may be caused in the operation of the CPU, such as operational abnormality of arithmetic logic unit (ALU), operational abnormality of a data path, operational abnormality of a register, operational abnormality of an internal RAM, operational abnormality of an address calculation, operational abnormality of interrupt processing, operational abnormality of control logic, and operational abnormality of a configuration register operational abnormality, is not dealt with by detecting this wide range of operational abnormality.
One countermeasure against a wide range of operational abnormality, which may be caused in the operation of the CPU, is a measure using a watchdog timer. For example, in the technique disclosed in, for example, Patent Document 2, a pulse signal is periodically supplied from the CPU to the watchdog timer to reset the watchdog timer. If the operational abnormality occurs to prevent the pulse signal from being supplied for a predetermined time duration, the watchdog timer outputs a reset signal to the CPU to cause the CPU to perform a reset process. Further, in the technique disclosed in Patent Document 3, the watchdog timer is provided in a manner similar to the Patent Document 2. However, if supply of a periodic watchdog timer clear signal is stopped, the watchdog timer determines that the CPU does not normally operate and send an error report to a higher-level system.